Cadence Releases XJTAG DFT Assistant for OrCAD Capture
Poster: SySAdmin
Posted on November 8, 2016 at 3:14:01 AM
Cadence Releases XJTAG DFT Assistant for OrCAD Capture
Software interface enables early detection and repair of circuit board errors at the design stage, before hardware is produced
SAN JOSE, Calif., Nov. 8, 2016 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its OrCAD(®) Capture has been enhanced to now include XJTAG(®) DFT Assistant, an easy-to-use interface that significantly increases the design for test (DFT) and debug capabilities of the schematic capture and PCB design system. Developed by boundary-scan hardware and software tool supplier XJTAG, XJTAG DFT Assistant allows users to detect and correct JTAG errors at the design stage before the PCB is produced, preventing costly re-spins and project delays. For more information, visit http://www.orcad.com/xjtag-orcad.
https://photos.prnewswire.com/prnvar/20140102/SF39436LOGO
"PCBs have become increasingly densely populated, and accessing pins under packages such as ball grid arrays (BGAs) has been virtually impossible," said Kishore Karnane, product management director, PCB Group, Cadence. "Boundary scan addresses this problem by providing electrical access to compliant integrated components on a PCB using a JTAG chain, but it is also imperative that any errors in the JTAG chain are corrected early. XJTAG DFT Assistant allows engineers to determine whether JTAG chains are correctly connected and terminated during schematic capture, early in the design process."
XJTAG DFT Assistant is composed of two key elements: XJTAG Chain Checker and XJTAG Access Viewer. XJTAG Chain Checker identifies common errors in a JTAG scan chain, such as incorrectly connected and terminated test access ports (TAPs), and reports them to the developer. Otherwise, a single connection error would inhibit the entire scan chain from working. XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, allowing users to instantly see which components are accessible using boundary scan, and where test coverage can be further extended. Engineers can highlight the nets individually to show read, write, power/ground and the nets without any JTAG access on the schematic.
"We need to determine early in the design phase how to maximize test coverage using the minimum number of test points, so it is vital to know what JTAG access is available at the schematic stage," said Urs Allemann, director of design services at ed electronic design ag. "The XJTAG DFT Assistant for OrCAD Capture makes it easy for us to see the test coverage as the design evolves. This allows us to optimize our testing before the PCB is produced."
While the first prototype is being manufactured, XJTAG DFT Assistant allows engineers to export a preliminary XJTAG project from OrCAD Capture to the XJTAG development software, where additional tests can be developed. Hardware can then be tested as soon as it is available.
XJTAG DFT Assistant software is now included with OrCAD Capture 17.2-2016 QIR 2 at no additional cost; users of version 17.2 or higher can download the software today from http://www.xjtag.com/orcad.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence(®) software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at http://www.cadence.com.
© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at http://www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective holders.
Cadence Newsroom
408-944-7039
newsroom@cadence.com
Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
SOURCE Cadence Design Systems, Inc.
Photo:https://photos.prnewswire.com/prnh/20140102/SF39436LOGO
http://photoarchive.ap.org/
Cadence Design Systems, Inc.
Web Site: http://www.cadence.com
Software interface enables early detection and repair of circuit board errors at the design stage, before hardware is produced
SAN JOSE, Calif., Nov. 8, 2016 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its OrCAD(®) Capture has been enhanced to now include XJTAG(®) DFT Assistant, an easy-to-use interface that significantly increases the design for test (DFT) and debug capabilities of the schematic capture and PCB design system. Developed by boundary-scan hardware and software tool supplier XJTAG, XJTAG DFT Assistant allows users to detect and correct JTAG errors at the design stage before the PCB is produced, preventing costly re-spins and project delays. For more information, visit http://www.orcad.com/xjtag-orcad.
https://photos.prnewswire.com/prnvar/20140102/SF39436LOGO
"PCBs have become increasingly densely populated, and accessing pins under packages such as ball grid arrays (BGAs) has been virtually impossible," said Kishore Karnane, product management director, PCB Group, Cadence. "Boundary scan addresses this problem by providing electrical access to compliant integrated components on a PCB using a JTAG chain, but it is also imperative that any errors in the JTAG chain are corrected early. XJTAG DFT Assistant allows engineers to determine whether JTAG chains are correctly connected and terminated during schematic capture, early in the design process."
XJTAG DFT Assistant is composed of two key elements: XJTAG Chain Checker and XJTAG Access Viewer. XJTAG Chain Checker identifies common errors in a JTAG scan chain, such as incorrectly connected and terminated test access ports (TAPs), and reports them to the developer. Otherwise, a single connection error would inhibit the entire scan chain from working. XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, allowing users to instantly see which components are accessible using boundary scan, and where test coverage can be further extended. Engineers can highlight the nets individually to show read, write, power/ground and the nets without any JTAG access on the schematic.
"We need to determine early in the design phase how to maximize test coverage using the minimum number of test points, so it is vital to know what JTAG access is available at the schematic stage," said Urs Allemann, director of design services at ed electronic design ag. "The XJTAG DFT Assistant for OrCAD Capture makes it easy for us to see the test coverage as the design evolves. This allows us to optimize our testing before the PCB is produced."
While the first prototype is being manufactured, XJTAG DFT Assistant allows engineers to export a preliminary XJTAG project from OrCAD Capture to the XJTAG development software, where additional tests can be developed. Hardware can then be tested as soon as it is available.
XJTAG DFT Assistant software is now included with OrCAD Capture 17.2-2016 QIR 2 at no additional cost; users of version 17.2 or higher can download the software today from http://www.xjtag.com/orcad.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence(®) software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at http://www.cadence.com.
© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at http://www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective holders.
Cadence Newsroom
408-944-7039
newsroom@cadence.com
Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
SOURCE Cadence Design Systems, Inc.
Photo:https://photos.prnewswire.com/prnh/20140102/SF39436LOGO
http://photoarchive.ap.org/
Cadence Design Systems, Inc.
Web Site: http://www.cadence.com