Cadence Announces DDR4 and LPDDR4 IP Achieve 3200 Mbps on TSMC 16nm FinFET Plus Process
Poster: SySAdmin
Posted on March 14, 2016 at 1:49:01 PM
Cadence Announces DDR4 and LPDDR4 IP Achieve 3200 Mbps on TSMC 16nm FinFET Plus Process
SAN JOSE, Calif., March 14, 2016 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its DDR4 and LPDDR4 IP products for TSMC's 16nm FinFET Plus (16FF+) process have completed TSMC9000 Silicon Assessment. The Cadence® Denali® DDR controller IP, and both the Denali DDR4 and LPDDR4 PHY IP, have demonstrated operating speeds of up to 3200 Mbps, and each are in production with several customers. Memory interface performance is crucial for alleviating the key system bottleneck of memory access, which can overshadow increases in processor performance. The high performance of Cadence's Denali DDR interface solutions supports the demanding data bandwidth requirements of various applications, including mobile, cloud computing and networking.
http://photos.prnewswire.com/prnvar/20140102/SF39436LOGO
The DDR4/3/3L controller and PHY IP have been validated with both dual in-line memory module (DIMM) and discrete DDR memory devices. This solution is popularly utilized in applications like servers, RAID storage, networking processors and several other networking ASICs. The LPDDR4/3 controller and PHY IP, on the other hand, have been validated with both package-on-package (POP) and discrete LPDDR memory devices. This IP solution is widely used in customer applications such as smartphones, tablets and automotive infotainment. The combination of the IP solutions' robust architecture, design guidelines and Cadence technical expertise has enabled customers to ramp their systems into volume production with DDR interfaces operating at speeds up to 3200 Mbps. For more information on DDR IP solutions, visit: http://www.cadence.com/news/DDRIP.
"We've combined our expertise with TSMC's technology to provide silicon-proven, advanced DDR IP solutions to our customers," said Hugh Durdan, vice president of design IP at Cadence. "By collaborating with TSMC on their 16FF+ process technology, Cadence enables customers to incorporate the latest DDR technology in their SoC projects while increasing their confidence in our IP solutions."
"Cadence is a leading IP supplier for TSMC's design ecosystem," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Through close collaboration, Cadence has developed IP for our 16FF+ advanced process node that meets the TSMC9000 silicon characterization criteria."
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.
© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and Denali are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com
Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
SOURCE Cadence Design Systems, Inc.
Photo:http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
http://photoarchive.ap.org/
Photo:http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
http://photoarchive.ap.org/
Cadence Design Systems, Inc.
Web Site: http://www.cadence.com
SAN JOSE, Calif., March 14, 2016 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its DDR4 and LPDDR4 IP products for TSMC's 16nm FinFET Plus (16FF+) process have completed TSMC9000 Silicon Assessment. The Cadence® Denali® DDR controller IP, and both the Denali DDR4 and LPDDR4 PHY IP, have demonstrated operating speeds of up to 3200 Mbps, and each are in production with several customers. Memory interface performance is crucial for alleviating the key system bottleneck of memory access, which can overshadow increases in processor performance. The high performance of Cadence's Denali DDR interface solutions supports the demanding data bandwidth requirements of various applications, including mobile, cloud computing and networking.
http://photos.prnewswire.com/prnvar/20140102/SF39436LOGO
The DDR4/3/3L controller and PHY IP have been validated with both dual in-line memory module (DIMM) and discrete DDR memory devices. This solution is popularly utilized in applications like servers, RAID storage, networking processors and several other networking ASICs. The LPDDR4/3 controller and PHY IP, on the other hand, have been validated with both package-on-package (POP) and discrete LPDDR memory devices. This IP solution is widely used in customer applications such as smartphones, tablets and automotive infotainment. The combination of the IP solutions' robust architecture, design guidelines and Cadence technical expertise has enabled customers to ramp their systems into volume production with DDR interfaces operating at speeds up to 3200 Mbps. For more information on DDR IP solutions, visit: http://www.cadence.com/news/DDRIP.
"We've combined our expertise with TSMC's technology to provide silicon-proven, advanced DDR IP solutions to our customers," said Hugh Durdan, vice president of design IP at Cadence. "By collaborating with TSMC on their 16FF+ process technology, Cadence enables customers to incorporate the latest DDR technology in their SoC projects while increasing their confidence in our IP solutions."
"Cadence is a leading IP supplier for TSMC's design ecosystem," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Through close collaboration, Cadence has developed IP for our 16FF+ advanced process node that meets the TSMC9000 silicon characterization criteria."
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.
© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and Denali are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com
Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
SOURCE Cadence Design Systems, Inc.
Photo:http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
http://photoarchive.ap.org/
Photo:http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
http://photoarchive.ap.org/
Cadence Design Systems, Inc.
Web Site: http://www.cadence.com