Mentor Graphics Launches Veloce Apps: Initiating the Next Era of Emulation
Poster: SySAdmin
Posted on February 25, 2016 at 9:28:01 AM
Mentor Graphics Launches Veloce Apps: Initiating the Next Era of Emulation
Highlights:
- New Veloce Apps target critical challenges in in-circuit emulation (ICE) debug, yield and manufacturing ramp-up, and gate-level verification.
- New era of emulation leverages applications-based strategy to quickly expand emulation use models for system-on-chip (SoC) and systems design verification.
- Application and operating system innovations accelerate compile, run time and debug cycle times for twice the overall throughput.
WILSONVILLE, Ore., Feb. 25, 2016 /PRNewswire/ -- Mentor Graphics Corp. (Nasdaq: MENT), today ushered in a new era of emulation by announcing new applications for the Veloce(®) emulation platform. The new Veloce Apps--Veloce Deterministic ICE, Veloce DFT and Veloce FastPath--overcome critical system-level verification challenges in complex SoC and system designs. They run on an upgraded Veloce OS3 operating system that significantly accelerates design compile cycles, gate-level flows, and the time it takes to review results ("time to visibility"). The combination of Veloce Apps on Veloce OS3 puts more capabilities into the hands of more engineers more quickly than hardware-centric strategies.
https://photos.prnewswire.com/prnvar/20160224/337082
Each of the new Veloce Apps addresses a specific verification issue:
-- Veloce Deterministic ICE overcomes unpredictability in ICE environments
by adding 100 percent visibility and repeatability for debug, and
provides access to other 'virtual-based' use models;
-- Veloce DFT accelerates Design for Test (DFT) verification prior to
tape-out to minimize the risk of catastrophic failure, and significantly
reduces run times when verifying designs after DFT insertion; and
-- Veloce FastPath optimizes emulation performance when verifying large
multi-clock SoC designs by enabling faster model execution speed.
These new Veloce Apps join Veloce Power, Veloce Enterprise Server and other apps in an expanding arsenal of software innovations for the Veloce emulation platform. Mentor will continue to expand the library of Veloce Apps to introduce new ways to ensure designs meet their functional and performance specifications on schedule.
The Veloce OS operating system adds software programmability and resource management to the Veloce platform, making it easier to add new use models that increase the ROI of the emulator. The recent upgrade of Veloce OS3 covers several innovations:
-- Integration of new High Performance Computing platforms cuts compile
time by 50 percent.
-- A faster gate-level flow operates as "plug-and-play"--able to accept
flat or hierarchical designs. This flow reduces the amount of memory
needed for compilation, which improves performance. By making it easier
to load and verify gate-level designs, the new flow improves confidence
in silicon fidelity.
-- The combination of software and hardware improvements spanning the run
time and debug cycles achieves 200 percent faster time-to-visibility.
These new Veloce emulation capabilities demonstrate how innovative software, running on powerful, qualified hardware and an extensible operating system, can target design risks faster than hardware-centric strategies. As emulation enters its fourth decade and expands across mainstream markets, the Veloce emulation platform has become a powerful resource across a range of hardware, software and system verification flows.
"Mentor continues to demonstrate its technology leadership through its application-based strategy for the Veloce emulation platform," said Eric Selosse, vice president and general manager of the Mentor Emulation Division. "These latest innovations accelerate overall verification throughput performance for our customers. The focus on software apps for specific SoC and system-level challenges is driving the future of emulation."
About the Veloce emulation platform
The Veloce emulation platform is a core technology in the Mentor(®) Enterprise Verification Platform(TM) (EVP) - a platform that boosts productivity in ASIC and SoC functional verification by combining advanced verification technologies in a comprehensive platform.
Now considered among the most versatile and powerful of verification tools, project teams use emulation for hardware debugging, hardware/software co-verification or integration, system-level prototyping, low-power verification and power estimation and performance characterization.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues for the fiscal year ending January 31, 2015, of approximately $1.2 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
For more information, please contact:
David Smith
Mentor Graphics
503.685.1135
david_smith@mentor.com
Mentor Graphics, Mentor and Veloce are registered trademarks, and Enterprise Verification Platform is a trademark, of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
http://photos.prnewswire.com/prnvar/20140317/AQ83812LOGO
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SOURCE Mentor Graphics Corporation
Photo:https://photos.prnewswire.com/prnh/20160224/337082
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Photo:http://photos.prnewswire.com/prnh/20140317/AQ83812LOGO
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Photo:https://photos.prnewswire.com/prnh/20160224/337082
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Photo:http://photos.prnewswire.com/prnh/20140317/AQ83812LOGO
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Mentor Graphics Corporation
Web Site: http://www.mentor.com
Highlights:
- New Veloce Apps target critical challenges in in-circuit emulation (ICE) debug, yield and manufacturing ramp-up, and gate-level verification.
- New era of emulation leverages applications-based strategy to quickly expand emulation use models for system-on-chip (SoC) and systems design verification.
- Application and operating system innovations accelerate compile, run time and debug cycle times for twice the overall throughput.
WILSONVILLE, Ore., Feb. 25, 2016 /PRNewswire/ -- Mentor Graphics Corp. (Nasdaq: MENT), today ushered in a new era of emulation by announcing new applications for the Veloce(®) emulation platform. The new Veloce Apps--Veloce Deterministic ICE, Veloce DFT and Veloce FastPath--overcome critical system-level verification challenges in complex SoC and system designs. They run on an upgraded Veloce OS3 operating system that significantly accelerates design compile cycles, gate-level flows, and the time it takes to review results ("time to visibility"). The combination of Veloce Apps on Veloce OS3 puts more capabilities into the hands of more engineers more quickly than hardware-centric strategies.
https://photos.prnewswire.com/prnvar/20160224/337082
Each of the new Veloce Apps addresses a specific verification issue:
-- Veloce Deterministic ICE overcomes unpredictability in ICE environments
by adding 100 percent visibility and repeatability for debug, and
provides access to other 'virtual-based' use models;
-- Veloce DFT accelerates Design for Test (DFT) verification prior to
tape-out to minimize the risk of catastrophic failure, and significantly
reduces run times when verifying designs after DFT insertion; and
-- Veloce FastPath optimizes emulation performance when verifying large
multi-clock SoC designs by enabling faster model execution speed.
These new Veloce Apps join Veloce Power, Veloce Enterprise Server and other apps in an expanding arsenal of software innovations for the Veloce emulation platform. Mentor will continue to expand the library of Veloce Apps to introduce new ways to ensure designs meet their functional and performance specifications on schedule.
The Veloce OS operating system adds software programmability and resource management to the Veloce platform, making it easier to add new use models that increase the ROI of the emulator. The recent upgrade of Veloce OS3 covers several innovations:
-- Integration of new High Performance Computing platforms cuts compile
time by 50 percent.
-- A faster gate-level flow operates as "plug-and-play"--able to accept
flat or hierarchical designs. This flow reduces the amount of memory
needed for compilation, which improves performance. By making it easier
to load and verify gate-level designs, the new flow improves confidence
in silicon fidelity.
-- The combination of software and hardware improvements spanning the run
time and debug cycles achieves 200 percent faster time-to-visibility.
These new Veloce emulation capabilities demonstrate how innovative software, running on powerful, qualified hardware and an extensible operating system, can target design risks faster than hardware-centric strategies. As emulation enters its fourth decade and expands across mainstream markets, the Veloce emulation platform has become a powerful resource across a range of hardware, software and system verification flows.
"Mentor continues to demonstrate its technology leadership through its application-based strategy for the Veloce emulation platform," said Eric Selosse, vice president and general manager of the Mentor Emulation Division. "These latest innovations accelerate overall verification throughput performance for our customers. The focus on software apps for specific SoC and system-level challenges is driving the future of emulation."
About the Veloce emulation platform
The Veloce emulation platform is a core technology in the Mentor(®) Enterprise Verification Platform(TM) (EVP) - a platform that boosts productivity in ASIC and SoC functional verification by combining advanced verification technologies in a comprehensive platform.
Now considered among the most versatile and powerful of verification tools, project teams use emulation for hardware debugging, hardware/software co-verification or integration, system-level prototyping, low-power verification and power estimation and performance characterization.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues for the fiscal year ending January 31, 2015, of approximately $1.2 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
For more information, please contact:
David Smith
Mentor Graphics
503.685.1135
david_smith@mentor.com
Mentor Graphics, Mentor and Veloce are registered trademarks, and Enterprise Verification Platform is a trademark, of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
http://photos.prnewswire.com/prnvar/20140317/AQ83812LOGO
Photo - http://photos.prnewswire.com/prnh/20160224/337082
Logo - http://photos.prnewswire.com/prnh/20140317/AQ83812LOGO
SOURCE Mentor Graphics Corporation
Photo:https://photos.prnewswire.com/prnh/20160224/337082
http://photoarchive.ap.org/
Photo:http://photos.prnewswire.com/prnh/20140317/AQ83812LOGO
http://photoarchive.ap.org/
Photo:https://photos.prnewswire.com/prnh/20160224/337082
http://photoarchive.ap.org/
Photo:http://photos.prnewswire.com/prnh/20140317/AQ83812LOGO
http://photoarchive.ap.org/
Mentor Graphics Corporation
Web Site: http://www.mentor.com