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Cadence Announces Broad Portfolio of 3D Memory Verification IP
Support for Early Adoption of Wide I/O 2, HMC, HBM and DDR4-3DS Standards
SAN JOSE, Calif., Oct. 23, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced the immediate availability of verification IP (VIP) supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS). The portfolio of memory VIP enables designers to accelerate the verification of memory interfaces and achieve earlier system-on-chip (SoC) verification closure for compute server applications, mobile devices, high-performance graphics and network applications.
http://photos.prnewswire.com/prnvar/20140102/SF39436LOGO
Advanced features of these new VIP models include direct memory access for read, write, save, preload and comparison of memory contents, robust assertions, error configurability, transaction callbacks, assertion reports and a built-in address manager. Additionally, the models support all leading third party simulators, verification languages and methodologies, enabling SoC verification teams with the fastest path to verify the correctness of interfaces to these new, specialized memories.
"Memory is a critical factor in increasing functionality and performance of advanced system topologies," said Robert Feurle, vice president of compute and networking marketing at Micron. "The fact that Cadence is involved in the development of all the latest standards enables our designers to accelerate their adoption of innovative technologies such as Hybrid Memory Cube."
"3D memories are increasingly becoming essential to the next generation of electronic products," said Erik Panu, vice president, Research & Development of the IP Group at Cadence. "The availability of Cadence VIP products supporting the latest standards facilitates a quick and convenient means for our customers to rapidly deploy the new 3D memory standards and to verify the correctness of their usage with SoC designs."
Information about the new products, along with articles and videos pertaining to 3D memory technologies is available at http://www.cadence.com/news/3dvip.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.
©2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com
Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
To view the original version on PR Newswire, visit:http://www.prnewswire.com/news-releases/cadence-announces-broad-portfolio-of-3d-memory-verification-ip-728313474.html
SOURCE Cadence Design Systems, Inc.
Photo:http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
http://photoarchive.ap.org/
Cadence Design Systems, Inc.
Web Site: http://www.cadence.com
Cadence Announces Broad Portfolio of 3D Memory Verification IP
Support for Early Adoption of Wide I/O 2, HMC, HBM and DDR4-3DS Standards
SAN JOSE, Calif., Oct. 23, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced the immediate availability of verification IP (VIP) supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS). The portfolio of memory VIP enables designers to accelerate the verification of memory interfaces and achieve earlier system-on-chip (SoC) verification closure for compute server applications, mobile devices, high-performance graphics and network applications.
http://photos.prnewswire.com/prnvar/20140102/SF39436LOGO
Advanced features of these new VIP models include direct memory access for read, write, save, preload and comparison of memory contents, robust assertions, error configurability, transaction callbacks, assertion reports and a built-in address manager. Additionally, the models support all leading third party simulators, verification languages and methodologies, enabling SoC verification teams with the fastest path to verify the correctness of interfaces to these new, specialized memories.
"Memory is a critical factor in increasing functionality and performance of advanced system topologies," said Robert Feurle, vice president of compute and networking marketing at Micron. "The fact that Cadence is involved in the development of all the latest standards enables our designers to accelerate their adoption of innovative technologies such as Hybrid Memory Cube."
"3D memories are increasingly becoming essential to the next generation of electronic products," said Erik Panu, vice president, Research & Development of the IP Group at Cadence. "The availability of Cadence VIP products supporting the latest standards facilitates a quick and convenient means for our customers to rapidly deploy the new 3D memory standards and to verify the correctness of their usage with SoC designs."
Information about the new products, along with articles and videos pertaining to 3D memory technologies is available at http://www.cadence.com/news/3dvip.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.
©2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com
Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
To view the original version on PR Newswire, visit:http://www.prnewswire.com/news-releases/cadence-announces-broad-portfolio-of-3d-memory-verification-ip-728313474.html
SOURCE Cadence Design Systems, Inc.
Photo:http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
http://photoarchive.ap.org/
Cadence Design Systems, Inc.
Web Site: http://www.cadence.com