Media Alert: Cadence to Demonstrate 16FF+ Design Solutions at TSMC 2014 OIP Ecosystem Forum

Media Alert: Cadence to Demonstrate 16FF+ Design Solutions at TSMC 2014 OIP Ecosystem Forum

SAN JOSE, Calif., Sept. 25, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced it is scheduled to demonstrate how it leverages the TSMC Open Innovation Platform(®) (OIP) to optimize customer designs and manufacturing efficiency to ensure first-time product success on the 16nm FinFET Plus (16FF+) process at TSMC 2014 OIP Ecosystem Forum. The event is being held on September 30, 2014 in San Jose, CA, and Cadence will be in booth #614.

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WHAT:
Cadence is scheduled to deliver the following presentations in the EDA and IP tracks:

    --  In-Design Signoff Key to Design Rule Check (DRC) Turnaround Time for
        16nm IC Designs: 11:00-11:30am, Esther Tsai, staff product engineer at
        Cadence
    --  10nm FEOL/MEOL Challenges and Process Development with Parasitic RC
        Extractions: 1:30-2:00pm, Hao Ji, software engineering group director at
        Cadence, and Sean Lee, deputy director at TSMC
    --  DDR4 Subsystem Implementation on 16FF/16FF+ Targeting Infrastructure
        Applications--Challenges and Design Techniques: 2:30-3:00pm, Anurag
        Jain, design engineering director at Cadence
    --  Tempus((TM))  Timing Signoff Solution for Certification in 16FF/10FF
        TSMC Flows: 4:00-4:30pm, Florentin Dartu, senior program manager at TSMC
    --  Managing 16FF IC Design Challenges for Custom and Analog Designers:
        4:30-5:00pm, Akshat Shah, product engineering director at Cadence
    --  Tackling Coloring, Cell Pin Access, Variability, and Late-Stage ECOs for
        TSMC 10nm with Cadence(®) Encounter(®) Digital Implementation System:
        5:00-5:30pm, Rahul Deokar and Ruben Molina, product marketing directors
        at Cadence
In addition, Cadence plans to showcase its 16FF+ design solutions in booth #614 including:

    --  Digital implementation solutions (front-end design (FED) and Encounter
        Digital Implementation System)
    --  Virtuoso(®) custom solutions
    --  Physical signoff and verification (PVS/DFM) solutions
    --  Electrical signoff solutions
    --  Custom/mixed-signal flow solutions
    --  3D-IC solutions
    --  DDR4 16FF PHY and controller IP solutions
To register for the conference, click here.

WHEN:
The TSMC 2014 OIP Ecosystem Forum is scheduled for September 30, 2014.

WHERE:

Santa Jose Convention Center in San Jose, CA

Cadence is located in booth #614.

About Cadence

Cadence (NASDAQ: CDNS) enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.

© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Encounter, and Virtuoso are registered trademarks and Tempus is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:

Cadence Newsroom

408-944-7039
newsroom@cadence.com

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SOURCE  Cadence Design Systems, Inc.

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Cadence Design Systems, Inc.

Web Site: http://www.cadence.com