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Tabula Releases 100G Ethernet Packet Parser Reference Design Kit
Spacetime 3D Architecture Enables a New Approach to L2-L4 Packet Parsing
SANTA CLARA, Calif., June 3, 2013 /PRNewswire/-- Tabula Inc., advancing high-performance programmable logic solutions for network infrastructure systems, today announced the availability of the latest addition to its suite of high-performance packet processing solutions: the 100G Ethernet Packet Parser Reference Design Kit. This latest kit is based on its new ABAX2P1 3PLD and supported by its Stylus revision 2.6.2 compiler.
The new 100 GbE packet parser represents a novel approach to this class of network functions, delivering a unique combination of programmability and low latency currently not achievable on a programmable device. It provides support for multiple L2 accesses and trunk frame formats and is easily scalable to support L3 and L4 parsing. It also benefits from a very small footprint - less than 2K LUTs for a single 100G stream, making it an extremely cost-effective and power-efficient programmable solution that can be extended to support multiple 100G streams on a single chip.
Tabula's Spacetime architecture enables designers to co-optimize performance and density. Combining programmable fabric in which all components can operate at 2 GHz with multi-port high-performance memories, this unique architecture opens the doors to design solutions that could not be explored before. In this 100 GbE packet parser reference design, these capabilities are used to parallelize the processing of multiple fields of an entire 100 GbE packet header, enabling the parsing function to be completed in a record 17 ns latency and making the parser software configurable to handle different L2 formats or extended to L3 and L4 parsing.
More about the 100 GbE packet parser
The 100 GbE packet parser includes the following features:
-- 149M packets/sec at the minimum packet size of 64 bytes
-- 100 GbE stream support at 100% efficiency
-- Deterministic latency of 17 ns
-- Guaranteed bandwidth of 122 Gbps
-- Less than 1.5 Watts per 100 GbE stream
Like the other reference design kits available in its suite of high-performance packet processing solutions, Tabula's 100 GbE packet parser kit is made available in source code form and comes complete with testbench, software toolkit and documentation.
Availability
Stylus revision 2.6.2 and the 100G Ethernet Packet Parser Reference Design Kit are available now and free of charge.
About Tabula
Tabula is the industry's most innovative programmable logic solutions provider, delivering breakthrough capabilities for today's most challenging systems applications. The company's ABAX(2) family of general-purpose 3D programmable logic devices (3PLDs), based on Tabula's patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at http://www.tabula.com
© 2013 Tabula, Inc. All rights reserved. Tabula, the Tabula logo, ABAX, the ABAX logo, Spacetime, the Spacetime logo, Stylus, the Stylus logo and other designated brands included herein are trademarks of Tabula, Inc. in the United States and other countries. All other trademarks are property of their respective owners
SOURCE Tabula Inc.
Tabula Inc.
CONTACT: Sabrina Joseph, Managing Partner, Morphoses, (408)236-7373, abulapr@morphoses.com
Web Site: http://www.tabula.com
Tabula Releases 100G Ethernet Packet Parser Reference Design Kit
Spacetime 3D Architecture Enables a New Approach to L2-L4 Packet Parsing
SANTA CLARA, Calif., June 3, 2013 /PRNewswire/-- Tabula Inc., advancing high-performance programmable logic solutions for network infrastructure systems, today announced the availability of the latest addition to its suite of high-performance packet processing solutions: the 100G Ethernet Packet Parser Reference Design Kit. This latest kit is based on its new ABAX2P1 3PLD and supported by its Stylus revision 2.6.2 compiler.
The new 100 GbE packet parser represents a novel approach to this class of network functions, delivering a unique combination of programmability and low latency currently not achievable on a programmable device. It provides support for multiple L2 accesses and trunk frame formats and is easily scalable to support L3 and L4 parsing. It also benefits from a very small footprint - less than 2K LUTs for a single 100G stream, making it an extremely cost-effective and power-efficient programmable solution that can be extended to support multiple 100G streams on a single chip.
Tabula's Spacetime architecture enables designers to co-optimize performance and density. Combining programmable fabric in which all components can operate at 2 GHz with multi-port high-performance memories, this unique architecture opens the doors to design solutions that could not be explored before. In this 100 GbE packet parser reference design, these capabilities are used to parallelize the processing of multiple fields of an entire 100 GbE packet header, enabling the parsing function to be completed in a record 17 ns latency and making the parser software configurable to handle different L2 formats or extended to L3 and L4 parsing.
More about the 100 GbE packet parser
The 100 GbE packet parser includes the following features:
-- 149M packets/sec at the minimum packet size of 64 bytes
-- 100 GbE stream support at 100% efficiency
-- Deterministic latency of 17 ns
-- Guaranteed bandwidth of 122 Gbps
-- Less than 1.5 Watts per 100 GbE stream
Like the other reference design kits available in its suite of high-performance packet processing solutions, Tabula's 100 GbE packet parser kit is made available in source code form and comes complete with testbench, software toolkit and documentation.
Availability
Stylus revision 2.6.2 and the 100G Ethernet Packet Parser Reference Design Kit are available now and free of charge.
About Tabula
Tabula is the industry's most innovative programmable logic solutions provider, delivering breakthrough capabilities for today's most challenging systems applications. The company's ABAX(2) family of general-purpose 3D programmable logic devices (3PLDs), based on Tabula's patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at http://www.tabula.com
© 2013 Tabula, Inc. All rights reserved. Tabula, the Tabula logo, ABAX, the ABAX logo, Spacetime, the Spacetime logo, Stylus, the Stylus logo and other designated brands included herein are trademarks of Tabula, Inc. in the United States and other countries. All other trademarks are property of their respective owners
SOURCE Tabula Inc.
Tabula Inc.
CONTACT: Sabrina Joseph, Managing Partner, Morphoses, (408)236-7373, abulapr@morphoses.com
Web Site: http://www.tabula.com