Tabula Sets New Industry Benchmarks with a Suite of 100G Programmable Solutions Based on the Company's ABAX2 P-Series of 3PLDs
Poster: SySAdmin
Posted on March 26, 2013 at 4:21:01 AM
Tabula Sets New Industry Benchmarks with a Suite of 100G Programmable Solutions Based on the Company's ABAX2 P-Series of 3PLDs
Unmatched capabilities resulting from the combination of four industry-leading technologies
SANTA CLARA, Calif., March 26, 2013 /PRNewswire/ -- Tabula Inc., advancing programmable logic solutions for network infrastructure systems, today announced a comprehensive suite of high-performance packet processing solutions. The suite solves the most challenging problems posed by the transition from 10 to 40G and 100G: specifically, routing of high-performance buses, on-chip RAM throughput, and timing closure for the ultra-high-performance functions required by these systems.
(Photo: http://photos.prnewswire.com/prnh/20130326/SF83415)
The packet processing solutions, combined with Tabula's new ABAX2P1 3PLD (the first of the ABAX2 P-Series), deliver unique capabilities such as the processing of four 100G streams on a single chip, a search engine capable of supporting 100G packet traffic, and a 12x10G-to-100G bridge. These breakthroughs are enabled by Tabula's industry-leading technologies in four key areas: 1) Programmable 3D architecture, 2) RTL compiler, 3) leading-edge process technology, and 4) 3PLD devices. Tabula will demonstrate its high-performance packet processing solutions during the company's first series of Spacetime Forums, beginning April 8(th). This series of one-day technical seminars will continue through May across a dozen cities in North America, Asia, and Europe. Over 250 engineers from key telecom and network system OEMs are expected to attend.
"With the migration from 10G to 40G and 100G, FPGA users are having a hard time delivering the kind of throughput needed by these systems," said Rich Wawrzyniak, Senior Market Analyst: ASIC & SoC, at Semico Research Corp. "With this set of programmable solutions, Tabula is demonstrating that their 3PLD can support four 100G streams on a single programmable device, something not achievable on other programmable solutions."
The high-performance packet processing reference design suite is composed of:
-- A 12x10G-to-100G bridge reference design kit, implementing an
aggregation function commonly used in communications systems and using
the ABAX2P1 device's unique high-performance bus-handling capabilities.
-- A 4x100G switch reference design kit, targeting data center migration
from 10G to 40G and 100G, is made possible by the ABAX2P1 device's
ability to process multiple 100G streams.
-- A 2(nd)-generation Ternary Search Engine (TSE) reference design kit,
delivering the high-performance search capabilities required for
leading-edge routers and NGFW while showcasing the ABAX2P1 device's
unmatched RAM capabilities.
To facilitate user design, the company also delivers a complete set of design examples and soft IP cores tailored for many of the most performance-critical functions found in high-performance packet processing equipment. Examples include a 600Gbps packet classifier, a 100Gbps 64-bit CRC generator, and a 1.3Tbps L2 packet parser.
"The capabilities we have demonstrated are simply out of reach of even the most advanced FPGAs," said Dennis Segers, Tabula's Chief Executive Officer. "With this comprehensive suite of programmable solutions, we are uniquely supporting the migration from 10G to 40G and 100G that is currently underway."
Tabula's four core technology components
-- The Spacetime 3D architecture employs time, rather than space, as a
third dimension, rapidly reprogramming every resource on the chip to
perform multiple, different functions per user cycle - up to 12 in the
current generation. Chips using Spacetime, called 3PLDs, are
nevertheless presented as having three spatial dimensions with all of
their resources distributed across 12 floors or folds, which
dramatically reduces die size vs. FPGAs. In addition, all components in
a 3PLD - logic, RAM, multiply/accumulate blocks, and interconnect -
operate in concert at up to 2 GHz, eliminating the performance
bottlenecks that exist in FPGAs.
-- The Stylus compiler integrates cutting-edge technologies, such as
sequential timing, router-aware placement, and automatic co-optimization
of performance and density to offer simpler, more intuitive RTL design
and a faster timing closure loop.
-- Tabula's partnership with Intel has provided for the manufacture of the
ABAX2 P-Series of devices on Intel's advanced 22nm Tri-Gate process. The
3D Tri-Gate transistors, the most advanced in the world, provide
unmatched speed at low operating voltage for reduced power. Production
scalability to meet the highest volume demands is supported via this key
alliance.
-- The ABAX2P1 3PLD is a 12-fold Spacetime device that delivers unique RAM
and logic fabric capabilities alongside tailored, hard IP blocks: a
combination that makes the chip and future members of the ABAX2 P-Series
well-suited for the most demanding packet processing applications.
By leveraging all four of these components, Tabula's high-performance packet processing suite provides a programmable solution that delivers industry-leading performance and can readily implement even the most challenging communications/network functions.
More about ABAX2P1
The ABAX2P1 3PLD integrates key capabilities that enable system designers to implement high-performance routers, switches, NGFW, and other communication systems. They include:
-- A programmable fabric supporting 2 GHz throughput through every
component of the chip - logic, RAM, MAC blocks, and interconnect
-- 23.3 Mbytes of 12- and 24-port on-chip memory delivering 13.8TB/s of
throughput - enough to support multiple 100G streams
-- Multiple, built-in, hard, DDR3 controllers operating at 2.133 GT/s, the
maximum DDR3 rate, delivering the bandwidth necessary to support
external packet buffering or storage of search tables for multiple 100G
streams
-- Multiple, built-in, hard, 100G Ethernet MACs to ensure easy timing
closure and low resource utilization of these ultra-high-performance
standard blocks
Availability
The initial set of high-performance packet processing solutions is incorporated in Stylus and is available now. Additional suite offerings are scheduled to be released on a monthly basis. Engineering samples of ABAX2P1 will be available in Q3.
About Tabula
Tabula is the industry's most innovative programmable logic solutions provider, delivering breakthrough capabilities for today's most challenging systems applications. The company's ABAX(2 )family of general-purpose 3D Programmable Logic Devices (3PLDs), based on Tabula's patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at http://www.tabula.com
© 2013 Tabula, Inc. All rights reserved. Tabula, the Tabula logo, ABAX(2), the ABAX(2) logo, Spacetime, the Spacetime logo, Stylus, the Stylus logo and other designated brands included herein are trademarks of Tabula, Inc. in the United States and other countries. All other trademarks are property of their respective owners
SOURCE Tabula Inc.
Photo:http://photos.prnewswire.com/prnh/20130326/SF83415
http://photoarchive.ap.org/
Tabula Inc.
CONTACT: Sabrina Joseph, Managing Partner, Morphoses, 560 S. Winchester Blvd., Suite 500, San Jose, CA, 95128, +1-408-236-7373, tabulapr@morphoses.com
Web Site: http://www.tabula.com
Unmatched capabilities resulting from the combination of four industry-leading technologies
SANTA CLARA, Calif., March 26, 2013 /PRNewswire/ -- Tabula Inc., advancing programmable logic solutions for network infrastructure systems, today announced a comprehensive suite of high-performance packet processing solutions. The suite solves the most challenging problems posed by the transition from 10 to 40G and 100G: specifically, routing of high-performance buses, on-chip RAM throughput, and timing closure for the ultra-high-performance functions required by these systems.
(Photo: http://photos.prnewswire.com/prnh/20130326/SF83415)
The packet processing solutions, combined with Tabula's new ABAX2P1 3PLD (the first of the ABAX2 P-Series), deliver unique capabilities such as the processing of four 100G streams on a single chip, a search engine capable of supporting 100G packet traffic, and a 12x10G-to-100G bridge. These breakthroughs are enabled by Tabula's industry-leading technologies in four key areas: 1) Programmable 3D architecture, 2) RTL compiler, 3) leading-edge process technology, and 4) 3PLD devices. Tabula will demonstrate its high-performance packet processing solutions during the company's first series of Spacetime Forums, beginning April 8(th). This series of one-day technical seminars will continue through May across a dozen cities in North America, Asia, and Europe. Over 250 engineers from key telecom and network system OEMs are expected to attend.
"With the migration from 10G to 40G and 100G, FPGA users are having a hard time delivering the kind of throughput needed by these systems," said Rich Wawrzyniak, Senior Market Analyst: ASIC & SoC, at Semico Research Corp. "With this set of programmable solutions, Tabula is demonstrating that their 3PLD can support four 100G streams on a single programmable device, something not achievable on other programmable solutions."
The high-performance packet processing reference design suite is composed of:
-- A 12x10G-to-100G bridge reference design kit, implementing an
aggregation function commonly used in communications systems and using
the ABAX2P1 device's unique high-performance bus-handling capabilities.
-- A 4x100G switch reference design kit, targeting data center migration
from 10G to 40G and 100G, is made possible by the ABAX2P1 device's
ability to process multiple 100G streams.
-- A 2(nd)-generation Ternary Search Engine (TSE) reference design kit,
delivering the high-performance search capabilities required for
leading-edge routers and NGFW while showcasing the ABAX2P1 device's
unmatched RAM capabilities.
To facilitate user design, the company also delivers a complete set of design examples and soft IP cores tailored for many of the most performance-critical functions found in high-performance packet processing equipment. Examples include a 600Gbps packet classifier, a 100Gbps 64-bit CRC generator, and a 1.3Tbps L2 packet parser.
"The capabilities we have demonstrated are simply out of reach of even the most advanced FPGAs," said Dennis Segers, Tabula's Chief Executive Officer. "With this comprehensive suite of programmable solutions, we are uniquely supporting the migration from 10G to 40G and 100G that is currently underway."
Tabula's four core technology components
-- The Spacetime 3D architecture employs time, rather than space, as a
third dimension, rapidly reprogramming every resource on the chip to
perform multiple, different functions per user cycle - up to 12 in the
current generation. Chips using Spacetime, called 3PLDs, are
nevertheless presented as having three spatial dimensions with all of
their resources distributed across 12 floors or folds, which
dramatically reduces die size vs. FPGAs. In addition, all components in
a 3PLD - logic, RAM, multiply/accumulate blocks, and interconnect -
operate in concert at up to 2 GHz, eliminating the performance
bottlenecks that exist in FPGAs.
-- The Stylus compiler integrates cutting-edge technologies, such as
sequential timing, router-aware placement, and automatic co-optimization
of performance and density to offer simpler, more intuitive RTL design
and a faster timing closure loop.
-- Tabula's partnership with Intel has provided for the manufacture of the
ABAX2 P-Series of devices on Intel's advanced 22nm Tri-Gate process. The
3D Tri-Gate transistors, the most advanced in the world, provide
unmatched speed at low operating voltage for reduced power. Production
scalability to meet the highest volume demands is supported via this key
alliance.
-- The ABAX2P1 3PLD is a 12-fold Spacetime device that delivers unique RAM
and logic fabric capabilities alongside tailored, hard IP blocks: a
combination that makes the chip and future members of the ABAX2 P-Series
well-suited for the most demanding packet processing applications.
By leveraging all four of these components, Tabula's high-performance packet processing suite provides a programmable solution that delivers industry-leading performance and can readily implement even the most challenging communications/network functions.
More about ABAX2P1
The ABAX2P1 3PLD integrates key capabilities that enable system designers to implement high-performance routers, switches, NGFW, and other communication systems. They include:
-- A programmable fabric supporting 2 GHz throughput through every
component of the chip - logic, RAM, MAC blocks, and interconnect
-- 23.3 Mbytes of 12- and 24-port on-chip memory delivering 13.8TB/s of
throughput - enough to support multiple 100G streams
-- Multiple, built-in, hard, DDR3 controllers operating at 2.133 GT/s, the
maximum DDR3 rate, delivering the bandwidth necessary to support
external packet buffering or storage of search tables for multiple 100G
streams
-- Multiple, built-in, hard, 100G Ethernet MACs to ensure easy timing
closure and low resource utilization of these ultra-high-performance
standard blocks
Availability
The initial set of high-performance packet processing solutions is incorporated in Stylus and is available now. Additional suite offerings are scheduled to be released on a monthly basis. Engineering samples of ABAX2P1 will be available in Q3.
About Tabula
Tabula is the industry's most innovative programmable logic solutions provider, delivering breakthrough capabilities for today's most challenging systems applications. The company's ABAX(2 )family of general-purpose 3D Programmable Logic Devices (3PLDs), based on Tabula's patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at http://www.tabula.com
© 2013 Tabula, Inc. All rights reserved. Tabula, the Tabula logo, ABAX(2), the ABAX(2) logo, Spacetime, the Spacetime logo, Stylus, the Stylus logo and other designated brands included herein are trademarks of Tabula, Inc. in the United States and other countries. All other trademarks are property of their respective owners
SOURCE Tabula Inc.
Photo:http://photos.prnewswire.com/prnh/20130326/SF83415
http://photoarchive.ap.org/
Tabula Inc.
CONTACT: Sabrina Joseph, Managing Partner, Morphoses, 560 S. Winchester Blvd., Suite 500, San Jose, CA, 95128, +1-408-236-7373, tabulapr@morphoses.com
Web Site: http://www.tabula.com