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Tabula Releases Groundbreaking EDA Technologies in Support of its Suite of High-Performance Packet Processing Solutions
High-performance designs made easy with Stylus compiler
SANTA CLARA, Calif., March 26, 2013 /PRNewswire/ -- Tabula Inc., advancing high-performance programmable logic solutions for network infrastructure systems, today announced the availability of its Stylus compiler revision 2.6, which supports the company's newly announced ABAX2P1 3D Programmable Logic Device (3PLD) and its suite of high-performance packet processing solutions.
The Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers and uses industry-standard RTL inputs and design constraints. It automatically exploits the unique advantages of Tabula's 3D Spacetime architecture, unleashing the ABAX(2) 3PLDs' unmatched capabilities and achieving unparalleled performance with surprising ease.
"The Stylus compiler enables designers to describe designs directly in terms of their intended latency and throughput without having to replicate logic or add lots of platform-specific implementation details just to meet performance," said Steve Teig, Tabula Founder and Chief Technical Officer. "The result is cleaner RTL that is not only simpler to verify but also easier to maintain and reuse."
More about the Stylus compiler
Stylus 2.6 integrates cutting-edge timing closure technologies including sequential timing, router-aware placement, and automatic co-optimization of performance and density.
-- Sequential timing typically enables timing closure within just a few
iterations. If a design fails to meet timing, Stylus shows the users not
just where but also why, so they know what to change to fix it. Using
sequential timing, Stylus reports multi-cycle feedback loops and paths
from input to output that are actually limiting a circuit's frequency,
rather than the single flop-to-flop paths that are often just artifacts
of imbalanced pipelines and not intrinsic limitations to the performance
of the design. Stylus automatically balances pipeline stages at
sub-nanosecond resolution, completely eliminating the tedious FPGA
design methodology of balancing pipelines manually, a methodology which
frequently fails to converge reliably to a timing-correct solution.
-- Stylus uses a novel routing-aware placement technology that provides
accurate interconnect delays and resource consumption tracking early in
the flow, thereby limiting downstream surprises from the router. This
early feedback enables a shorter timing-closure loop, allowing designers
to achieve high performance results faster and more easily.
-- Stylus automates the co-optimization of performance and density that
3PLDs uniquely enable. It automatically selects the optimum number of
folds for each clock domain independently,and where appropriate,
replicates functional blocks to achieve the specified throughput. Thus,
Stylus frees the user to specify just the desired latency and throughput
without the need to parallelize the design manually to achieve high
performance.
In addition, to help users take full advantage of the ABAX2P1 device's unmatched embedded RAM capacity and throughput, Stylus transparently infers multi-ported memories (up to 24-ports) from RTL, automatically packing small user memories and folding wide user memories into the device's on-chip RAM blocks.
Availability
Stylus 2.6 is available now.
Accelerating Worldwide Deployment
Tabula will demonstrate Stylus 2.6 together with its new high-performance packet processing solution suite during the company's first Spacetime Forum. This series of one-day technical seminars will commence on April 8(th) and continue through May across a dozen cities in North America, Asia, and Europe. More than 250 engineers from key telecom OEMs are expected to attend.
About Tabula
Tabula is the industry's most innovative programmable logic solutions provider, delivering breakthrough capabilities for today's most challenging systems applications. The company's ABAX(2 )family of general-purpose 3D Programmable Logic Devices (3PLDs), based on Tabula's patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at http://www.tabula.com
© 2013 Tabula, Inc. All rights reserved. Tabula, the Tabula logo, ABAX(2), the ABAX(2) logo, Spacetime, the Spacetime logo, Stylus, the Stylus logo and other designated brands included herein are trademarks of Tabula, Inc. in the United States and other countries. All other trademarks are property of their respective owners
SOURCE Tabula Inc.
Tabula Inc.
CONTACT: Sabrina Joseph, Managing Partner, Morphoses, 560 S. Winchester Blvd., Suite 500, San Jose, CA 95128, Tel: +1-408-236-7373, tabulapr@morphoses.com
Web Site: http://www.tabula.com
Tabula Releases Groundbreaking EDA Technologies in Support of its Suite of High-Performance Packet Processing Solutions
High-performance designs made easy with Stylus compiler
SANTA CLARA, Calif., March 26, 2013 /PRNewswire/ -- Tabula Inc., advancing high-performance programmable logic solutions for network infrastructure systems, today announced the availability of its Stylus compiler revision 2.6, which supports the company's newly announced ABAX2P1 3D Programmable Logic Device (3PLD) and its suite of high-performance packet processing solutions.
The Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers and uses industry-standard RTL inputs and design constraints. It automatically exploits the unique advantages of Tabula's 3D Spacetime architecture, unleashing the ABAX(2) 3PLDs' unmatched capabilities and achieving unparalleled performance with surprising ease.
"The Stylus compiler enables designers to describe designs directly in terms of their intended latency and throughput without having to replicate logic or add lots of platform-specific implementation details just to meet performance," said Steve Teig, Tabula Founder and Chief Technical Officer. "The result is cleaner RTL that is not only simpler to verify but also easier to maintain and reuse."
More about the Stylus compiler
Stylus 2.6 integrates cutting-edge timing closure technologies including sequential timing, router-aware placement, and automatic co-optimization of performance and density.
-- Sequential timing typically enables timing closure within just a few
iterations. If a design fails to meet timing, Stylus shows the users not
just where but also why, so they know what to change to fix it. Using
sequential timing, Stylus reports multi-cycle feedback loops and paths
from input to output that are actually limiting a circuit's frequency,
rather than the single flop-to-flop paths that are often just artifacts
of imbalanced pipelines and not intrinsic limitations to the performance
of the design. Stylus automatically balances pipeline stages at
sub-nanosecond resolution, completely eliminating the tedious FPGA
design methodology of balancing pipelines manually, a methodology which
frequently fails to converge reliably to a timing-correct solution.
-- Stylus uses a novel routing-aware placement technology that provides
accurate interconnect delays and resource consumption tracking early in
the flow, thereby limiting downstream surprises from the router. This
early feedback enables a shorter timing-closure loop, allowing designers
to achieve high performance results faster and more easily.
-- Stylus automates the co-optimization of performance and density that
3PLDs uniquely enable. It automatically selects the optimum number of
folds for each clock domain independently,and where appropriate,
replicates functional blocks to achieve the specified throughput. Thus,
Stylus frees the user to specify just the desired latency and throughput
without the need to parallelize the design manually to achieve high
performance.
In addition, to help users take full advantage of the ABAX2P1 device's unmatched embedded RAM capacity and throughput, Stylus transparently infers multi-ported memories (up to 24-ports) from RTL, automatically packing small user memories and folding wide user memories into the device's on-chip RAM blocks.
Availability
Stylus 2.6 is available now.
Accelerating Worldwide Deployment
Tabula will demonstrate Stylus 2.6 together with its new high-performance packet processing solution suite during the company's first Spacetime Forum. This series of one-day technical seminars will commence on April 8(th) and continue through May across a dozen cities in North America, Asia, and Europe. More than 250 engineers from key telecom OEMs are expected to attend.
About Tabula
Tabula is the industry's most innovative programmable logic solutions provider, delivering breakthrough capabilities for today's most challenging systems applications. The company's ABAX(2 )family of general-purpose 3D Programmable Logic Devices (3PLDs), based on Tabula's patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at http://www.tabula.com
© 2013 Tabula, Inc. All rights reserved. Tabula, the Tabula logo, ABAX(2), the ABAX(2) logo, Spacetime, the Spacetime logo, Stylus, the Stylus logo and other designated brands included herein are trademarks of Tabula, Inc. in the United States and other countries. All other trademarks are property of their respective owners
SOURCE Tabula Inc.
Tabula Inc.
CONTACT: Sabrina Joseph, Managing Partner, Morphoses, 560 S. Winchester Blvd., Suite 500, San Jose, CA 95128, Tel: +1-408-236-7373, tabulapr@morphoses.com
Web Site: http://www.tabula.com